MX Foundation 4
ASCB Introduction

The Avionics Standard Communications Bus is a relatively old protocol that was developed by Honeywell in the 80’s. It provides data processing and transfer rate of 2/3 Mps on a bi-directional bus that supports up to 50 users (version C).

Three versions of ASCB are supported. Version A, the oldest, has the following characteristics:

  • Two systems alternate in the role of bus controller
  • Separate clock and data lines are used

Version B of the ASCB bus differs in two ways from the Version A bus:

  • A full time bus controller is used
  • Clock lines are not used

Version C of the ASCB bus differs in the following ways from the Version B bus:

  • The bus users contain Very Large Scale Integration (VLSI) hardware which permits them to simultaneously transmit and receive data. This feature enables the Version C bus loading to be twice as dense as Version B.
  • In general, the Version C bus system utilizes four bus lines (two primary and two backup buses) to attain CRITICAL level status. At least one Category 2 program (GV) uses a mixture of two and four buses resulting in a less critical system.
  • Version C users have new back shell pin out requirements to ensure physical spacing of ASCB connections.
  • Some users have been added to and some deleted from the Version B scheme.

MX Foundation supports all three flavors of ASCB without requiring knowledge of which one is implemented by the user. The differences between each variation of ASCB is in terms of characteristics that can be individually turned on and off.

The combination of those features/characteristics determines which one of the ASCB variants is actually implemented. In addition, it is also possible to create hybrid forms of ASCB, which may reveal itself very useful in a test environment.

The table below summarizes the characteristics supported by MX Foundation as features. Those characteristics/features can be enabled on an individual basis.

Characteristic A B C1 C2
2 buses and 2 bus controllers X X
BC starts on constant idle bus time X X
B1-B2 clocks (clock mode) X
BC transfer (XFER CONTROL) X
C1 BC status message X
C1 frame timing X
C2 BC status message X
C2 frame timing X
4 buses and 4 bus controllers X X
BC starts on variable idle bus time
based on dynamic priority
X X
Bus synchronization pattern X X
Updated 10/23/2023