For each HDLC/SDLC channel, a corresponding CLOCK channel must exists. For HDLC/SDLC on FlexMAX SMP module, the HDLC/SDLC and CLOCK channels are fixed, so nothing has to be done. On multi module, HDLC/SDLC [0] must have a CLOCK channel at position [4], HDLC/SDLC [1] with CLOCK [5], and so on. The protocol selection is made with the mxfSystemInitAttributeUint64CallbackHandler() function or with the KMXF_CHANNEL_CLASS attribute.

Usually, the RX HDLC channel clock source is external and the TX HDLC channel clock source is internal. When the internal loopback is enabled, the clock source attribute becomes read-only.

The clock frequency is set by using the HDLC Internal Clock Frequency attribute.

For the transmitter channel, when the clock source is set to internal, the clock will come from the internal free-running clock and will be sent on the corresponding CLOCK channel. When the clock source is external, the clock will come from the corresponding CLOCK channel. The clock is transmitted from the moment the HDLC transmitter is enabled until it is disabled.

For the receiver channel, when the clock source is set to internal, the clock will come from the internal free-running clock. When the clock source is external, the clock will come from the corresponding CLOCK channel.

The clock electrical attributes (e.g. voltage, offset, etc.) can also be modified.

When KMXF_HDLC_DATA_ENCODING is set to VMXF_HDLC_ENCODING_MANCHESTER_NOCLK, the CLOCK channel must still be assigned, but it will not be used.